1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory employing direct-type sense amplifiers capable of realizing high-speed access.
2. Description of the Related Art
Recent semiconductor technology has allowed development of high-speed, high-integrated semiconductor memories such as dynamic random access memories (DRAMs). Of these memories, synchronous DRAMs (SDRAMs) operate in synchronization with an external clock signal to improve the operation speed thereof and to realize pipeline operations therein.
Some semiconductor memories (SDRAMs) employ direct-type sense amplifiers and select them for data write with the use of column selection lines running in parallel with bit lines and write-only column selection lines running orthogonally to the column selection lines. Note that the direct-type sense amplifier can be constituted to separate bit lines (BL, /BL) from an input/output side, and therefore, is appropriate for achieving pipeline processes in the memory. Further, the semiconductor memories usually employ a multiple-bit data width instead of a conventional single bit data width.
By the way, a memory controller handles data between the memory and a CPU (Central Processing Unit) byte by byte. Namely, the minimum unit of data handled between the memory and the CPU is a byte. Nevertheless, to transfer data at high speed, the memory and CPU must be connected to each other through a wide data bus of, for example, 16 bits (two bytes) or 32 bits (four bytes).
In this way, broadening a data width to larger than a minimum data unit (one byte) handled by the memory controller is advantageous in handling data of large width. This, however, is disadvantageous when handling data of narrow width, less than eight bits (one byte), because each piece of data must have bits equal to the unit data width. To avoid a useless operation, some semiconductor memories have a masking function. This function works on each minimum data unit (one byte) handled by the memory controller. Note that, in the prior art semiconductor memories, the masking function causes a delay in a column selection operation, and such delay is an obstacle to improve the operation speed of the memory, and therefore, must be minimized.
Further, there is a requirement for the semiconductor memory (SDRAM) to provide a technique and layout for efficiently controlling the write-only column selection lines.
Prior art and the problems thereof will be explained later with reference to accompanying drawings.